The present invention relates generally to semiconductor design technology, and more particularly, to a system and method for providing an improved main amplifier and an input-output bus for use with a dynamic random access memory.
Speed and timing constraints have always been important considerations in designing electronic systems. Most system designs must match the timing requirements of all the components used, yet still be optimized for high speed. As a result, many integrated circuits, or "chips," utilize a synchronous design. A synchronous chip is one in which components of the chip are connected to a common system clock. Synchronous chips typically have latches, registers and/or counters connected to some of its inputs and outputs, all on a single monolithic chip. Furthermore, synchronous chips provide many benefits to system designers, such as fewer external logic chips and high speed operation.
One example of a synchronous chip is a synchronous dynamic random access memory ("SDRAM"). In concept, a SDRAM is simply a dynamic random access memory ("DRAM") with registers and/or latches included on the same chip. However, circuit and bus designs become more critical as the number of transistors and the speed of the transistors increase. For example, there exists conventional 16 Mbit SDRAMs (1 Mbit equals 1,048,576 memory cells, or "bits") as well as 64 Mbit DRAMs. However, presently, no 64 Mbit SDRAM exists. One convenient method for creating 64 Mbit SDRAMs is by combining the peripheral circuitry (circuits peripheral to a memory cell array) used in the 16 Mbit SDRAM with the memory array of the 64 Mbit DRAM. However, such a combination, due to higher operating speed required by the synchronous operation and heavier capacitive loads due to the increase in memory cells, creates a new set of problems. One such problem is timing conflicts. Timing conflicts may result in incorrect data being read and possibly making the device inoperable. Another problem is voltage level discrepancies. Voltage level discrepancies may result in signals being connected to different power supplies, thereby shorting the power supplies. As a result, power consumption is increased and reliability problems such as high temperature and current flow are prevalent.
To illustrate these problems, a 64 Mbit DRAM and a 16 Mbit SDRAM will be discussed. The 64 Mbit DRAM separates memory cells into a discrete number of banks. For the sake of example, four banks will be used. Associated with each of the banks of memory cells are a plurality of main amplifiers including a main amplifier circuit discussed below with reference to FIG. 1. Also associated with each of the banks of memory cells are a plurality of write amplifiers including a write amplifier circuit discussed below with reference to FIG. 2. Both the main amplifier and write amplifier are derived from the 16 Mbit SDRAM.
FIG. 1 describes a main amplifier circuit 10 for the 16 Mbit SDRAM. The main amplifier circuit 10 receives a plurality of signals including a bank activate signal MASJ, a main input-output separate signal MACBJ, a main amplifier activation signal MAEJ, a test signal MATESTB, and a main amplifier precharge signal MAPJ. The main amplifier also drives three signals: a main input-output signal MIOT, an inverted main input-output signal MIOB, and a main amplifier output MOJ. Furthermore, the main amplifier circuit 10 is connected to power supplies including a positive external power supply VDD, a negative external power supply VSS, and a positive power supply V.sub.1. In the 16 Mbit SDRAM, the power supply V.sub.1 is equal to VDD, but for reasons that will become more evident with the discussion below, for the present description, these two power supplies will be distinguished.
The main amplifier circuit 10 can be separated into four different sections. A first section, represented by a NAND gate 12, receives the two signals MASJ and MACBJ. The MASJ signal remains "high" whenever the main amplifier circuit 10 is "active". The main amplifier circuit 10 is active whenever it is being used to access a memory cell in its associated bank of memory cells. The MACBJ signal transitions "low" whenever the amplifier should be separating the two output signals MIOT and MIOB. Circuitry used to separate the two output signals is not shown, but different implementation of such circuitry are well known by those of ordinary skill in the art. Because the MASJ signal remains high, the NAND gate 12 has an output N1 that is an inverted signal of the MACBJ signal.
A second section of the main amplifier circuit 10 is a precharge circuit 14. The precharge circuit 14 precharges the output signals MIOB and MIOT by connecting them together and to VDD or V.sub.1 for specific periods of time. Precharging is controlled by the MAPJ signal when the two output signals MIOT and MIOB are not being separated, and by the MASJ signal when the bank associated with the main amplifier circuit 10 is not active.
A third section of the main amplifier circuit 10 is a flip flop 16. The flip flop 16 receives the N1 signal as well as a signal N2 derived from the precharge circuit 14. The flip flop produces two output signals N3 and N4.
A fourth section of the main amplifier circuit 10 is a drive circuit 18. The drive circuit 18 receives the outputs N3 and N4 of the flip flop 16 to selectively drive an output signal MOJ of a main output bus.
In addition, the drive circuit 18 receives the MATESTB signal, which signifies that the main amplifier circuit 10 is in a test mode. The test mode is used during production testing of the 16 Mbit SDRAM to shorten test times. To test the 16 Mbit SDRAM, each memory cell must be accessed. Utilizing a test mode allows more than one memory cell to be written to and read from at the same time, thereby reducing the test time. The 16 Mbit SDRAM has 16 MOJ signals grouped to form the main output bus, in order to facilitate a 16 bit wide SDRAM. Furthermore, the 16 Mbit SDRAM has 16 main amplifier circuits. Therefore, the 16 Mbit SDRAM may simultaneous access sixteen memory locations, thereby improving the test time. In order to improve test times further, it would be advantageous to access more than 16 memory cells at the same time.
FIG. 2 describes a write amplifier circuit 20 for the 16 Mbit SDRAM. The write amplifier circuit 20 receives a plurality of signals including a first precharge signal MIPTIJ, a second precharge signal MIPBIJ, an equalization signal MIEQIJ, a first write signal MDIB, and a second write signal MDIT. The write amplifier circuit 20 also drives the main and inverted input-output signals MIOT and MIOB. Furthermore, the write amplifier circuit 20 is connected to the negative external power supply VSS and a positive internal power supply V.sub.1, which equals VDD.
The write amplifier circuit 20 can equalize the output signals MIOB and MIOT by connecting them together and/or to V.sub.1 for specific periods of time. Furthermore, the write amplifier circuit 20 can selectively drive the output signals MIOB and MIOT to either V.sub.1 or VSS by appropriately asserting the write signals MDIB, MDIT, MIPBIJ, or MIPTIJ.
The 64 Mbit DRAM has a memory array that operates at an intermediate voltage level, which is between VDD and VSS. The intermediate voltage level is required for a variety of reasons, well known by those of ordinary skill in the art. A problem arises when the above two amplifier circuits from the 16 Mbit SDRAM, which operate at VDD and VSS, are combined with the 64 Mbit memory cell array which requires the intermediate voltage. A first solution is to change the voltage level for VDD. However, this solution does not work because other peripheral circuits, as well as other peripheral chips, require the voltage level for VDD to be at a higher, predefined level. A second solution is to change the positive internal power supply V.sub.1 to be equal to the intermediate voltage level. In this way, the voltage level for VDD remains the same, and the intermediate voltage level for the memory array is reduced. However, this solution creates a new set of problems, as discussed below.
FIG. 3 shows a timing diagram representing the signals and circuits discussed above, and illustrating an example of the problems caused by the different voltage levels VDD and V.sub.1. The functionality of the input signals is basically a function of other circuits included with the 16 Mbit SDRAM, but not shown. It is understood, however, that one of ordinary skill in the art will be familiar with the input signals and their accompanying waveform, with reference to the signal descriptions provided above.
The waveform for the N1 signal is basically an inversion of the waveform for the MACBJ signal whenever the main amplifier circuit 10 is activated (MASJ is high), as shown by the reference arrows 22, 24, 26, 28. In so doing, the N1 signal simply notifies the main amplifier circuit 10 when separation is to occur. The main amplifier is capable of driving the output signals MIOB and MIOT, referenced generally by MIOx, whenever the N1 signal is low. Therefore, referring to the reference arrows 30, 32 and 34, when the MAPJ signal is low, the main amplifier circuit 10 drives the MIOx signals to VDD. Likewise, referring to the reference arrows 36 and 38, the write amplifier circuit 20 also drives the MIOx signals to V.sub.1 or VSS at specific times. However, during times 40 and 42, both the main amplifier circuit 10 and the write amplifier circuit 20 are driving the MIOx signals at the same time but to different voltage levels. Since the MIOx signals will not be at two different voltages at the same time, a "short" exists, for a limited period of time, between the corresponding power supplies. In order to improve the reliability and power consumption of the 64 Mbit SDRAM, it would be advantageous to eliminate any shorts between the power supplies.